Regular Session 7
Description
Affiliation: Tallinn University of Technology (EE)
Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron Classifiers
Affiliations: 1 Karlsruhe Institute of Technology (DE), 2 University of Patras (GR), 3 RevoAI GmbH (DE)
Printed Electronics (PE) is an emerging technology with flexible substrates and ultra-low-cost manufacturing, providing an appealing alternative to traditional wafer-scale silicon fabrication. With the increasing integration of various printed neural network (NN) architectures in diverse applications, the reliability of printed circuits has become a critical concern. This work provides a comprehensive analysis of the fault sensitivity on a variety of classification tasks for various digital and analog realizations of printed multilayer perceptrons (MLPs). We further evaluate different digital architectures, i.e., generic, bespoke, and approximate, to provide a comprehensive fault analysis on different benchmark datasets.
Priyanjana Pal received her B.Tech. in ECE from NIT Agartala in 2018 and M.Tech. in EE from IIT Gandhinagar in 2020. She worked as a Senior ESD engineer at Global Foundries, Bangalore for nearly three years. In 2022, she joined as a PhD researcher with Prof. Mehdi Tahoori's group at Karlsruhe Institute of Technology(KIT), Germany. Her current research interests are in circuit design with CAD tools, reliability testing of printed circuits, and designing ML-trained flexible neuromorphic circuits.
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth
Affiliations: 1 University of Bremen (DE), 2 DFKI (DE)
In the context of digital circuits, formal verification methods have been well-studied to ensure their functional correctness. However, several verification methods fail to provide an upper bound for the time and space complexity. Therefore, Polynomial Formal Verification (PFV) has been introduced to address this problem. Unlike prior works, which have shown that approximate circuits can be verified in polynomial time, we show that approximate circuits with a constant cutwidth can be verified even in linear time. Since approximate circuits have become ubiquitous in error-resilient applications, it becomes essential to guarantee their correctness. While prior works have been limited to formal error analysis, we use Answer Set Programming (ASP) based formal verification to guarantee that the approximate circuit matches its functional specification. In this paper, we first show that several approximate adder circuits exhibit a constant cutwidth. We then provide a PFV approach that relies on this cutwidth as a structural property of the circuits to guarantee a linear-time verification w.r.t. the bitwidth using ASP. Finally, we evaluate several approximate adders in terms of the upper bound of the cutwidth, and verification time.
Mohamed Nadeem is a PhD student in Computer Architecture group under the supervision of Prof. Rolf Drechsler at the University of Bremen. Prior to that, he completed my Master's degree in Computational logic at Techincal University of Dresden, where he was working in the Knowledge Representation and Human Reasoning Group. His Research interests are Knowledge Representation, Logic Synthesis, and Polynomial Formal Verification.